Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics

Abstract Fault Emulation on FPGA: A Feasibility Study

This paper describes a feasibility study of accelerating fault simulation by emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to further speed up simulation, we propose to make use of reconfigurable hardware by emulating circuit together with fault insertion structures on FPGA. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms. 1

Environment for Fault Simulation Acceleration on FPGA

We present an environment to accelerate fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. We studied the feasibility of using reconfigurable hardware emulator instead of software simulation. Experiments showed that it is beneficial to use emulation for circuits /methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms

Evaluating fault emulation on FPGA

Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to evaluate possible simulation speed possibilities, we made a feasibility study of using reconfigurable hardware by emulating circuit under analysis together with fault insertion structures on FPGA. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms. 1

Fast Fault Emulation for Synchronous Sequential Circuits

ABSTRACT: Current paper presents an approach to emulate fault simulation of sequential circuits on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In the paper, we explain the problems associated to fault emulation for sequential circuits. Two alternative approaches are described, which can be considered as trade-offs in terms of required FPGA resources and fault grading accuracy. In addition, an environment for reconfigurable hardware emulation of fault simulation is proposed. Experiments show that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g. simulation-based test pattern generation or validation

Abstract FPGA Based Fault Emulation of Synchronous Sequential Circuits

This paper describes a feasibiliiy siudy of accelerating fault simulation by emulation on FPGA. Fault simulation b an important subtask in test pattem generation and it isfiequently used throughout the test generation process. In order to further speed up simulalion, we propose to make use of reconjgurable hardware by emulating cir-cuit together with fault insertion siructures on FPGA. Experiments showed that it is beneficial to use emulation for circuitdmethoak that require large numbers of test vectors, e.g., sequential circuits and/or genetic algo-rithms. 1

Rejuvenation of nbti-impacted processors using evolutionary generation of assembler programs

The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits implemented with current nanotechnology nodes. NBTI increases the threshold voltage of pMOS transistors: hence' it slows down signal propagation along logic paths between flip-flops. It may cause intermittent faults and' ultimately' permanent functional failures in processor circuits. In this paper' we study an NBTI mitigation approach in processor designs by rejuvenation of pMOS transistors along NBTI-critical paths. The method incorporates hierarchical fast' yet accurate modelling of NBTI-induced delays at transistor' gate and path levels for generation of rejuvenation Assembler programs using an Evolutionary Algorithm. These programs are applied further as an execution overhead to drive those pMOS transistors to the recovery phase' which are the most critical for the NBTI-induced path delay in processors. The experimental results demonstrate efficiency of evolutionary generation and significant reduction of NBTI-induced delays by the rejuvenation stimuli with an execution overhead of 0.1% or less. The proposed approach aims at extending the reliable lifetime of nanoelectronic processors

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics